1. Field of the Invention
The present invention generally relates to verifying circuit designs and, more particularly, to functionally verifying a physical device under test.
2. Description of the Related Art
The field of electronic design automation (EDA) is well established. A number of software tools are used to describe a circuit at various levels of granularity or specificity. Such tools include gate level descriptions, which specify the circuit in very great detail, to high level descriptions written in hardware description languages (HDLs), such as VERILOG or VHDL. Design verification is the process of determining whether an integrated circuit, board, or system-level architecture, exactly implements the requirements defined by the specification of the architecture for that device. As designs become more complex, the likelihood of design errors increases and design verification becomes increasingly difficult and time consuming.
Presently, design verification for a device under test (DUT) is performed on a simulation model of the device. A conventional process of verifying a design through a simulation model of the device is aided by the availability of HDLs. The resultant simulated model of the device receives input stimuli in the form of test vectors, which may be a string of binary digits applied to the input of a circuit. The simulated model then produces results, which are checked against expected results for the particular design of the device. Since HDLs are typically not designed for actual verification, a verification engineer must write additional programming code to interface with the models described by these HDLs in order to perform design verification of the device.
In some cases, it is desirable to perform design verification on an actual, physical device (e.g., an integrated circuit). Verification of an actual device should not be confused with testing an actual device. Devices are conventionally tested after being manufactured to determine whether they are operative. As discussed above, design verification is the process of checking that a design functions according to the specification of the design. Verifying an actual device is more complex than verifying a simulation model of the device. Notably, the actual device runs many orders of magnitude faster than a simulation model of the device (e.g., on the order of a million times faster). Thus, the application of test vectors and analysis of the results becomes nontrivial. In addition, it is difficult and impractical to monitor the internal nodes of a design in the actual device, whereas such internal nodes are accessible in a simulation model.
Accordingly, there exists a need in the art for a method and apparatus for functionally verifying a physical device under test.